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8-7 military 5.0v pasic 1 family - very-high-speed cmos fpga military 5.0v pasic 1 family rev b military 5.0v pasic 1 family device highlights very high speed vialink? metal-to-metal programmable technol- ogy, allows counter speeds over 150 mhz and logic cell delays of under 2 ns at 5v, and over 80 mhz at 3.3v operation. high usable density up to a 24-by-32 array of 768 logic cells provides 22,000 usable pld gates in 208-pin pqfp and 208-pin cqfp packages. pci-output drive fully pci 2.1 compliant input/output capability. (including drive current) features total of 180 i/o pins -172 bidirectional input/output pins -6 dedicated input/high-drive pins -2 clock/dedicated input pins with fanout- independent, low-skew clock networks -pci 2.1 compliant i/os input + logic cell + output delays under 6 ns chip-to-chip operating frequencies up to 110 mhz internal state machine frequencies up to 150 mhz clock skew < 0.5 ns input hysteresis provides high noise immunity built-in scan path permits 100% factory testing of logic and i/o cells and functional testing with auto- matic test vector generation (atvg) software after programming 208 pin pqfp pin for pin compatible with the 208 cqfp 0.65 cmos process with vialink programming technology table 1: selector table d evice h ighlights f eatures device asic gates pld gates package max i/o qualification level smd 5962- ql8x12b 1,000 2,000 68cpga 64 m ql12x16b 2,000 4,000 84cpga 76 m, /883 96836 144cpga 122 m, /883 95599 ql16x24b 4,000 7,000 160 cqfp 122 m, /883 95599 208cqfp 180 m, /883 96837 ql24x32b 8,000 14,000 208pqfp 180 m m = military temperature (-55 to +125 degrees c) /883 = mil-std-883 qualified
8 preliminary 8-8 military 5.0v pasic 1 family product summary the pasic 1 family is a very-high-speed cmos user-programmable asic devices. the 768 logic cell field-programmable gate array (fpga) features 22,000 usable pld gates of high-performance gen- eral-purpose logic in a 208-pin pqfp and cqfp package. low-impedance, metal-to-metal, vialink intercon- nect technology provides nonvolatile custom logic capable of operating above 150 mhz. logic cell delays under 2 ns, combined with input delays of under 1.5 ns and output delays under 3 ns, permit high-density programmable devices to be used with today?s fastest microprocessors and dsps. designs can be entered using quicklogic?s quick- works toolkit or most popular third-party cae tools. quickworks combines verilog/vhdl design entry and simulation tools with device-specific place & route and programming software. ample on-chip routing channels allow fast, fully automatic place and route of designs using up to 100% of the logic and i/ o cells, while maintaining fixed pin-outs. pinout diagram 68-pin cpga table 2: cpga 68 function/connector pin table p roduct s ummary p inout d iagram 68-p in cpga pin func pin func pin func pin func b10iob2iok2iok10 io a10 io b1 io l2 io k11 io b9 io c2 io k3 io j10 io a9 io c1 io l3 io j11 io b8 io d2 io k4 io h10 io a8 io d1 io l4 io h11 io b7 i/(sclk) e2 io k5 i/(si) g10 io a7 i/clk/(sm) e1 io l5 i/clk g11 io b6 vcc f2 gnd k6 vcc f10 gnd a6 i f1 io l6 i f11 io b5 i g2 io k7 i/(so) e10 io a5 io g1 io l7 io e11 io b4 io h2 io k8 io d10 io a4 io h1 io l8 io d11 io b3 io j2 io k9 io c10 io a3 io j1 io l9 io c11 io a2 io k1 io l10 io b11 io
8-9 military 5.0v pasic 1 family pinout diagram 84-pin cpga table 3: cpga 84 function/connector pin table p inout d iagram 84-p in cpga pin func pin func pin func pin func b10iob2iok2iok10io b9 io c2 io k3 io j10 io a10 io b1 io l2 io k11 io a9 io c1 io l3 io j11 io b8 io d2 io k4 io h10 io a8 io d1 io l4 io h11 io a7 io e1 io l5 io g11 io c7 gnd e3 gnd j5 gnd g9 gnd a6 io e2 io l6 io g10 io b7 i/(sclk) f1 io k5 i/(si) f11 io c6 i/clk/(sm) f2 io j6 i/clk f10 io b6 i(p) f3 io k6 i f9 io b5 i g1 io k7 i/(so) e11 io c5 vcc g3 vcc j7 vcc e9 vcc a5 io g2 io l7 io e10 io a4 io h1 io l8 io d11 io b4 io h2 io k8 io d10 io a3 io j1 io l9 io c11 io a2 io k1 io l10 io b11 io b3 io j2 io k9 io c10 io a1 io l1 io l11 io a11 io
10 preliminary 8-10 military 5.0v pasic 1 family pinout diagram 144-pin cpga table 4: cpga 144 function/connector table (cont?d on next page) p inout d iagram 144-p in cpga pin func pin func pin func pin func a2 io b15 io r14 io p1 io b3 io c14 io p13 io n2 io c4 io d13 io n12 io m3 io a3 io c15 io r13 io n1 io b4 io d14 io p12 io m2 io a4 io e13 vcc r12 io l3 vcc c3 vcc d15 io n13 vcc m1 io b5 io e14 io p11 io l2 io a5 io e15 io r11 io l1 io c6 io f13 io n10 io k3 io b6 io f14 io p10 io k2 io a6 io f15 io r10 io k1 io a7 io g15 io r9 io j1 io b7 io c13 gnd p9 io n3 gnd c5 gnd g14 io n11 gnd j2 io a8ioh15ior8ioh1io b8 i/(sclk) h14 io p8 i/(si) h2 io c8 i/clk/(sm) g13 gnd n8 i/clk j3 gnd c7 vcc h13 io n9 vcc h3 io a9 i/(p) j15 io r7 i g1 io b9 i j14 io p7 i/(so) g2 io c11 vcc j13 vcc n5 vcc g3 vcc a10 io k15 io r6 io f1 io a11 io l15 io r5 io e1 io b10 io k14 io p6 io f2 io
8-11 military 5.0v pasic 1 family cpga 144 function/connector table (cont?d ) a12 io m15 io r4 io d1 io b11 io l14 io p5 io e2 io c10 io k13 io n6 io f3 io a13 io n15 io r3 io c1 io c9 gnd l13 gnd n7 gnd e3 gnd b12 io m14 io p4 io d2 io a14 io p15 io r2 io b1 io b13 io n14 io p3 io c2 io c12 io m13 io n4 io d3 io a15 io r15 io r1 io a1 io b14 io p14 nc p2 io b2 nc p inout d iagram 160-p in cpga ql16x24b-1cf160m
12 preliminary 8-12 military 5.0v pasic 1 family pinout diagram 208-pin cpga p inout d iagram 208-p in cpga ql24x32b-1pq208m pasic pin #1 pin #157 pin #53 pin #105
8-13 military 5.0v pasic 1 family pqfp/cqfp 208 function/connector table pqfp/cqfp 208 f unction / connector t able pin fun pin fun pin fun pin fun pin fun pin fun pin fun pin fun 1 i/o 27 vcc 53 i/o 79 i/o 105 i/o 131 vcc 157 i/o 183 i/o 2 i/o 28 i/p 54 i/o 80 i/o 106 i/o 132 i 158 i/o 184 i/o 3 i/o 29 i 55 i/o 81 i/o 107 i/o 133 i/so 159 i/o 185 i/o 4 i/o 30 vcc 56 i/o 82 i/o 108 i/o 134 vcc 160 i/o 186 i/o 5 i/o 31 i/o 57 i/o 83 vcc 109 i/o 135 i/o 161 i/o 187 vcc 6 i/o 32 i/o 58 i/o 84 i/o 110 i/o 136 i/o 162 i/o 188 i/o 7 i/o 33 i/o 59 gnd 85 i/o 111 i/o 137 i/o 163 gnd 189 i/o 8 i/o 34 i/o 60 i/o 86 i/o 112 i/o 138 i/o 164 i/o 190 i/o 9 i/o 35 i/o 61 vcc 87 i/o 113 i/o 139 i/o 165 vcc 191 i/o 10 vcc 36 i/o 62 i/o 88 i/o 114 vcc 140 i/o 166 i/o 192 i/o 11 i/o 37 i/o 63 i/o 89 i/o 115 i/o 141 i/o 167 i/o 193 i/o 12 gnd 38 i/o 64 i/o 90 i/o 116 gnd 142 i/o 168 i/o 194 i/o 13 i/o 39 i/o 65 i/o 91 i/o 117 i/o 143 i/o 169 i/o 195 i/o 14 i/o 40 i/o 66 i/o 92 i/o 118 i/o 144 i/o 170 i/o 196 i/o 15 i/o 41 vcc 67 i/o 93 i/o 119 i/o 145 vcc 171 i/o 197 i/o 16 i/o 42 i/o 68 i/o 94 i/o 120 i/o 146 i/o 172 i/o 198 i/o 17 i/o 43 gnd 69 i/o 95 gnd 121 i/o 147 gnd 173 i/o 199 gnd 18 i/o 44 i/o 70 i/o 96 i/o 122 i/o 148 i/o 174 i/o 200 i/o 19 i/o 45 i/o 71 i/o 97 vcc 123 i/o 149 i/o 175 i/o 201 vcc 20 i/o 46 i/o 72 i/o 98 i/o 124 i/o 150 i/o 176 i/o 202 i/o 21 i/o 47 i/o 73 gnd 99 i/o 125 i/o 151 i/o 177 gnd 203 i/o 22 i/o 48 i/o 74 i/o 100 i/o 126 i/o 152 i/o 178 i/o 204 i/o 23 gnd 49 i/o 75 i/o 101 i/o 127 gnd 153 i/o 179 i/o 205 i/o 24 i/o 50 i/o 76 i/o 102 i/o 128 i/o 154 i/o 180 i/o 206 i/o 25 i/sck 51 i/o 77 i/o 103 i/o 129 i/si 155 i/o 181 i/o 207 i/o 26 i/clk 52 i/o 78 gnd 104 i/o 130 i/clk 156 i/o 182 gnd 208 i/o
14 preliminary 8-14 military 5.0v pasic 1 family absolute maximum ratings supply voltage ........................-0.5 to 7.0v input voltage................ -0.5 to vcc +0.5v esd pad protection .................... 2000v dc input current .......................20 ma latch-up immunity .................. 200 ma storage temperature .......-65 c to +150 c lead temperature ...........................300 c 5 volt operating range dc characteristics over 5v operating range notes: [1] capacitance is sample tested only. ci = 20 pf max on i/(si). [2] only one output at a time. duration should not exceed 30 seconds. [3] maximum icc for military grade is 20 ma. for ac conditions use the formula described in the databook, section 9 - power vs operating frequency. [4] stated timing for worst case propagation delay over process variation at vcc = 5.0v and ta = 25 c. mul- tiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. [5] these limits are derived from a representative selection of the slowest paths through the pasic logic cell including net delays. worst case delay values for specific paths should be determined from timing analysis of your particular design. symbol parameter military unit min max vcc supply voltage 4.5 5.5 v ta ambient temperature -55 c tc case temperature 125 c k delay factor -0 speed grade 0.39 1.82 -1 speed grade 0.39 1.56 symbol parameter conditions min max unit vih input high voltage 2.0 v vil input low voltage 0.8 v ioh = -4 ma 3.7 v voh output high voltage ioh = 16 ma 2.4 v ioh = -10 a vcc-0.1 v vol output low voltage iol = 8 ma 0.4 v iol = 10 a 0.1 v ii input leakage current vi = vcc or gnd -10 10 a ioz 3-state output leakage current vi = vcc or gnd -10 10 a ci input capacitance [1] 10 pf ios output short circuit current [2] vo = gnd -10 -90 ma vo = vcc 40 160 ma icc d.c. supply current [3] vi, vio = vcc or gnd 20 ma
8-15 military 5.0v pasic 1 family ql8x12b ac characteristics at vcc = 5v, ta = 25 c (k = 1.00) logic cell input cells output cell notes: [6] see high drive buffer table for more information. [7] clock buffer fanout refers to the maximum number of flip flops per half column. the number of half columns used does not affect clock buffer delay. [8] the following loads are used for tpxz: ql8 x 12b propagation delays (ns) symbol parameter fanout 12348 tpd combinatorial delay [5] 1.7 2.1 2.6 3.0 4.8 tsu setup time [5] 2.1 2.1 2.1 2.1 2.1 th hold time 0.0 0.0 0.0 0.0 0.0 tclk clock to q delay 1.0 1.5 1.9 2.3 4.2 tcwhi clock high time 2.0 2.0 2.0 2.0 2.0 tcwlo clock low time 2.0 2.0 2.0 2.0 2.0 tset set delay 1.7 2.1 2.6 3.0 4.8 treset reset delay 1.5 1.8 2.2 2.5 3.9 tsw set width 1.9 1.9 1.9 1.9 1.9 trw reset width 1.8 1.8 1.8 1.8 1.8 symbol parameter propagation delays (ns) [4] 123468 tin high drive input delay [6] 2.1 2.2 2.3 2.4 2.6 2.9 tini high drive input, inverting delay [6] 2.1 2.2 2.3 2.5 2.8 3.1 tio input delay (bidirectional pad) 1.4 1.8 2.2 2.6 3.4 4.2 tgck clock buffer delay [7] 2.7 2.7 2.8 2.9 3.0 tgckhi clock buffer min high [7] 2.0 2.0 2.0 2.0 2.0 tgcklo clock buffer min low [7] 2.0 2.0 2.0 2.0 2.0 propagation delays (ns) [4] symbol parameter output load capacitance (pf) 30 50 75 100 150 toutlh output delay low to high 2.7 3.4 4.2 5.0 6.7 touthl output delay high to low 2.8 3.7 4.7 5.6 7.6 tpzh output delay tri-state to high 4.0 4.9 6.1 7.3 9.7 tpzl output delay tri-state to low 3.6 4.2 5.0 5.8 7.3 tphz output delay high to tri-state [8] 2.9 tplz output delay low to tri-state [8] 3.3
16 preliminary 8-16 military 5.0v pasic 1 family high drive buffer [4] stated timing for worst case propagation delay over process variation at vcc = 5.0v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. clock drivers propagation delays (ns) [4] symbol parameter wired together fanout 12 24 48 72 96 14.04.9 tin high drive input delay 2 3.5 5.0 3 4.0 4.8 5.6 44.14.8 14.25.1 tini high drive input, 2 3.7 5.2 inverting delay 3 4.2 5.0 5.8 44.35.0
8-17 military 5.0v pasic 1 family ql12x16b ac characteristics at vcc = 5v, ta = 25 c (k = 1.00) logic cell input cells output cell notes: [6] see high drive buffer table for more information. [7] clock buffer fanout refers to the maximum number of flip flops per half column. the number of half col- umns used does not affect clock buffer delay. [8] the following loads are used for tpxz: ql12 x 16b propagation delays (ns) symbol parameter fanout 12348 tpd combinatorial delay [5] 1.7 2.2 2.6 3.2 5.2 tsu setup time [5] 2.1 2.1 2.1 2.1 2.1 th hold time 0.0 0.0 0.0 0.0 0.0 tclk clock to q delay 1.0 1.5 1.9 2.5 4.6 tcwhi clock high time 2.0 2.0 2.0 2.0 2.0 tcwlo clock low time 2.0 2.0 2.0 2.0 2.0 tset set delay 1.7 2.1 2.6 3.2 5.2 treset reset delay 1.5 1.9 2.2 2.7 4.3 tsw set width 1.9 1.9 1.9 1.9 1.9 trw reset width 1.8 1.8 1.8 1.8 1.8 symbol parameter propagation delays (ns) [4] 123468 tin high drive input delay [6] 2.4 2.5 2.6 2.7 3.0 3.3 tini high drive input, inverting delay [6] 2.5 2.6 2.7 2.8 3.1 3.4 tio input delay (bidirectional pad) 1.4 1.9 2.2 2.8 3.7 4.6 tgck clock buffer delay [7] 2.7 2.8 2.8 2.9 2.9 3.0 tgckhi clock buffer min high [7] 2.0 2.0 2.0 2.0 2.0 2.0 tgcklo clock buffer min low [7] 2.0 2.0 2.0 2.0 2.0 2.0 propagation delays (ns) [4] symbol parameter output load capacitance (pf) 30 50 75 100 150 toutlh output delay low to high 2.7 3.4 4.2 5.0 6.7 touthl output delay high to low 2.8 3.7 4.7 5.6 7.6 tpzh output delay tri-state to high 4.0 4.9 6.1 7.3 9.7 tpzl output delay tri-state to low 3.6 4.2 5.0 5.8 7.3 tphz output delay high to tri-state [8] 2.9 tplz output delay low to tri-state [8] 3.3
18 preliminary 8-18 military 5.0v pasic 1 family high drive buffer [4] stated timing for worst case propagation delay over process variation at vcc = 5.0v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. clock drivers propagation delays (ns) [4] symbol parameter wired together fanout 12 24 48 72 96 14.55.4 tin high drive input delay 2 3.9 5.6 3 4.5 5.3 6.3 44.65.3 14.75.6 tini high drive input, 2 4.0 5.8 inverting delay 3 4.6 5.5 6.4 44.85.5
8-19 military 5.0v pasic 1 family ql16x24b ac characteristics at vcc = 5v, ta = 25 c (k = 1.00 ) logic cell input cells output cell notes: [6] see high drive buffer table for more information. [7] clock buffer fanout refers to the maximum number of flip flops per half column. the number of half col- umns used does not affect clock buffer delay. [8] the following loads are used for tpxz: ql16 x 24b propagation delays (ns) symbol parameter fanout 12348 tpd combinatorial delay [5] 1.7 2.2 2.6 3.2 5.3 tsu setup time [5] 2.1 2.1 2.1 2.1 2.1 th hold time 0.0 0.0 0.0 0.0 0.0 tclk clock to q delay 1.0 1.5 1.9 2.6 4.7 tcwhi clock high time 2.0 2.0 2.0 2.0 2.0 tcwlo clock low time 2.0 2.0 2.0 2.0 2.0 tset set delay 1.7 2.2 2.6 3.2 5.3 treset reset delay 1.5 1.9 2.2 2.7 4.4 tsw set width 1.9 1.9 1.9 1.9 1.9 trw reset width 1.8 1.8 1.8 1.8 1.8 symbol parameter propagation delays (ns) [4] 123468 tin high drive input delay [6] 2.8 2.9 3.0 3.1 4.0 5.3 tini high drive input, inverting delay [6] 3.0 3.1 3.2 3.3 4.1 5.7 tio input delay (bidirectional pad) 1.4 1.9 2.2 2.9 4.7 6.5 tgck clock buffer delay [7] 2.7 2.8 2.9 3.0 3.1 3.3 tgckhi clock buffer min high [7] 2.0 2.0 2.0 2.0 2.0 2.0 tgcklo clock buffer min low [7] 2.0 2.0 2.0 2.0 2.0 2.0 propagation delays (ns) [4] symbol parameter output load capacitance (pf) 30 50 75 100 150 toutlh output delay low to high 2.7 3.4 4.2 5.0 6.7 touthl output delay high to low 2.8 3.7 4.7 5.6 7.6 tpzh output delay tri-state to high 4.0 4.9 6.1 7.3 9.7 tpzl output delay tri-state to low 3.6 4.2 5.0 5.8 7.3 tphz output delay high to tri-state [8] 2.9 tplz output delay low to tri-state [8] 3.3
20 preliminary 8-20 military 5.0v pasic 1 family high drive buffer [4] stated timing for worst case propagation delay over process variation at vcc = 5.0v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as spec- ified in the operating range. clock drivers propagation delays (ns) [4] symbol parameter wired together fanout 12 24 48 72 96 15.36.7 tin high drive input delay 2 4.5 6.6 3 5.3 6.2 7.2 45.46.2 15.77.2 tini high drive input, 2 4.6 6.8 inverting delay 3 5.5 6.4 7.4 45.66.4
8-21 military 5.0v pasic 1 family ql24x32b a c characteristics at vcc = 5v, ta = 25 c (k = 1.00) logic cell input cells output cell notes: [6] see high drive buffer table for more information. [7] clock buffer fanout refers to the maximum number of flip flops per half column. the number of half columns used does not affect clock buffer delay. [8] the following loads are used for tpxz: ql24 x 32b propagation delays (ns) symbol parameter fanout 12348 tpd combinatorial delay [5] 1.7 2.1 2.7 3.3 5.5 tsu setup time [5] 2.1 2.1 2.1 2.1 2.1 th hold time 0.0 0.0 0.0 0.0 0.0 tclk clock to q delay 1.0 1.5 1.9 2.7 4.9 tcwhi clock high time 2.0 2.0 2.0 2.0 2.0 tcwlo clock low time 2.0 2.0 2.0 2.0 2.0 tset set delay 1.7 2.2 2.7 3.3 5.5 treset reset delay 1.5 1.9 2.3 2.8 4.6 tsw set width 1.9 1.9 1.9 1.9 1.9 trw reset width 1.8 1.8 1.8 1.8 1.8 symbol parameter propagation delays (ns) [4] 123481216 tin high drive input delay [6] 3.1 3.2 3.3 3.4 4.4 5.8 6.5 tini high drive input, inverting delay [6] 3.3 3.4 3.5 3.6 4.6 6.0 6.7 tio input delay (bidirectional pad) 1.4 1.9 2.3 3.0 4.8 6.7 8.5 tgck clock buffer delay [7] 2.7 2.8 2.9 3.0 3.1 3.3 3.4 tgckhi clock buffer min high [7] 2.0 2.0 2.0 2.0 2.0 2.0 2.0 tgcklo clock buffer min low [7] 2.0 2.0 2.0 2.0 2.0 2.0 2.0 propagation delays (ns) [4] symbol parameter output load capacitance (pf) 30 50 75 100 150 toutlh output delay low to high 2.7 3.3 3.8 4.3 5.4 touthl output delay high to low 2.8 3.6 4.5 5.3 6.9 tpzh output delay tri-state to high 2.1 2.6 3.1 3.7 4.8 tpzl output delay tri-state to low 2.6 3.3 4.1 4.9 6.5 tphz output delay high to tri-state [8] 2.9 tplz output delay low to tri-state [8] 3.3
22 preliminary 8-22 military 5.0v pasic 1 family high drive buffer [4] stated timing for worst case propagation delay over process variation at vcc = 5.0v and ta = 25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature set- tings as specified in the operating range. ac performance propagation delays depend on routing, fanout, load capacitance, supply voltage, junction temperature, and process variation. the ac characteristics are a design guide to provide initial timing estimates at nominal conditions. worst case estimates are obtained when nominal propagation delays are multi- plied by the appropriate delay factor, k, as specified in the delay factor table (operating range). the effects of voltage and temperature variation are illus- trated in the graphs on the following pages, k factor versus voltage and temperature. the pasic devel- opment tools incorporate data sheet ac character- istics into the qdif database for pre-place-and-route timing analysis. the spde delay modeler extracts specific timing parameters for precise path analysis or simulation results following place and route. ordering information clock drivers propagation delays (ns) [4] symbol parameter wired together fanout 12 24 48 72 96 15.87.2 tin high drive input delay 2 5.0 7.1 3 5.8 6.7 7.7 45.96.8 16.07.4 tini high drive input, 2 5.2 7.3 inverting delay 3 6.0 6.9 7.9 46.17.0 ql 24x32b - 1 cf208 m quicklogic pasic device pasic device part number b = 0.65 micron cmos 8x12b 12x16b 16x24b 24x32b operating range m = military m/883c = mil std 883 package code cg68 = 68-pin cpga cg84 = 84-pin cpga cg144 = 144-pin cpga cf160 = 160-pin cqfd pq208 = 208-pin pqfp cf208 = 208-pin cqfp speed grade 0 = fast 1 = faste r

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